It is well known that a CCD is a semiconductor device that can store signal charges near the surface of a semiconductor substrate and transfer said signal charges in succession. On the other hand, a CMD is described in the invention of U.S. Pat. No. 5,337,340 published on Aug. 9, 1994, and it is a semiconductor device that uses a CCD and can realize a charge multiplication or signal amplification function inside the CCD cell.
FIG. 10 is a diagram illustrating the constitution of a CMD. As shown in the figure, as the basic unit of the CMD or CMD unit UCMD, a plurality (say, 4) electrodes G1, G2, G3, G4 are set in a row via an insulating film, such as silicon oxide film 100, on a silicon substrate. Driving voltages P1, P2, P3, P4 with phase and cycle relationships shown in FIG. 11 are applied on said electrodes G1, G2, G3, G4, respectively. Among these driving voltages, P1, P2, P4 are applied as pulse voltages for clock operation, and P3 is applied as a DC voltage at a prescribed level. Here, a characteristic feature is that with respect to electrode G4, driving voltage P4 has an H-level voltage (VCMG) much higher than other driving voltages P1, P2, P3. As an example, when P1 and P2 are set at an H level of 5 V and L level of −4 V, and P3 is set at 0 V (ground potential), P4 is set at an H level (VCMG) of 14 V and L level of 1.5 V.
When driving voltage P2 is at the H level while driving voltage P1 is at the L level, as shown in FIG. 10, the signal charge on the surface of the silicon substrate moves from beneath electrode G1 to beneath electrode G2, and pixel separation barrier 102 with a shallow potential is formed beneath electrode G1, and, at the same time, temporary storage well 104 with a relatively large depth is formed beneath electrode G2. In this case, charge transfer barrier 106 with a potential a little deeper than that of said pixel separation barrier 102 is formed beneath electrode G3.
In this state, when driving voltage P4 is changed from the L level to the H level, charger collection well 108 is formed beneath electrode G4 as a very deep well, with a depth several times that of said temporary storage well 104. Then, when P2 is changed from the H level to the L level right after that, the potential of temporary storage well 104 rises to reach the level indicated by broken line 104′. Then, the signal charge stored in temporary storage well 104 right beneath electrode G2 is drawn through above charge transfer barrier 106 into charge collection well 108 right beneath electrode G4 under a high electric field in the lateral direction, that is, the transfer direction, and it forcibly impacts silicon atoms (Si) in said well 108 to generate secondary electrons of electron-hole pairs. That is, co-called impact ionization takes place. Among the electron-hole pairs generated in said impact ionization, the holes are drawn to the deep portion of the silicon substrate or the nearby electrode, and the electrons are left in charge collection well 108.
In this way, charge multiplication takes place in charge collection well 108. Then, although not shown in the figure, when driving voltage P1 is changed from the L level to the H level, temporary storage well 104 is formed beneath electrode G1. As driving voltage P4 is changed from the H level to the L level right after that, the bottom of charge collection well 108 rises, and it becomes shallower even than temporary storage well 104. As a result, the signal charge moves from charge collection well 108 to beneath electrode G1. After that, the aforementioned operation is carried out repeatedly.
In this way, as driving voltages (pulses) P1, P2, P4 having the same cycle or period and synchronized under a common clock are applied with a prescribed phase difference on corresponding electrodes P1, P2, P4, respectively, in CMD unit UCMD, transfer and charge multiplication are performed for a pixel in each cycle.
In the conventional CMD, plural sections of said CMD units UCMD (G1, G2, G3, G4) are set (repeatedly) in the charge transfer direction, and, in each unit UCMD, charge multiplication is performed by means of said impact ionization in each cycle. Consequently, the signal charge passing through the CMD is subject to impact ionization (charge multiplication) for the same number of rounds as the number of sections (total number) of CMD units UCMD. In said conventional CMD, in order to control the overall signal amplification rate of the CMD, control is performed to change the H level voltage (VCMG) of driving voltage P4 as the bias voltage of the charge collection well with respect to electrode G4.
Consequently, as shown in FIG. 12, the charge multiplication rate of the CMD displays a characteristic curve that rises steeply with respect to the bias voltage of charge collection well (VCMG), and, in the range where a high amplification rate is obtained, even a small change in the bias voltage (VCMG) leads to a significant change in the amplification rate. Consequently, fine control of the signal amplification rate by means of voltage control becomes very hard.
The objective of this invention is to solve the aforementioned problems of the conventional method by providing a type of CMD and a type of CMD-carrying CCD device characterized by the fact that control of the signal amplification rate can be carried out simply and with high precision.